(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method and structure of creating an inductor as part of a semiconductor device in such a manner that a negative impact of via resistance is sharply reduced.
(2) Description of the Prior Art
Integrated Circuits (IC""s) are typically formed in or on the surface of a semiconductor substrate, electrical circuit elements of the individual IC""s are connected internally to the semiconductor surface on which the IC""s are formed. IC""s that are formed in or on the surface of a substrate are mostly active digital processing devices but can also include analog processing devices. In addition, discrete passive components can be formed that function with active semiconductor devices and that are preferably created using semiconductor device technology procedures and equipment.
One of the major challenges in the creation of analog processing circuitry using digital processing procedures and equipment is that a number of components used for analog circuitry are large in size and are therefore not easy to integrate into devices that typically have feature sizes approaching the sub-micron range. The main components that offer a challenge in this respect are capacitors and inductors, both these components are, for typical analog processing circuitry, of considerable size.
A typical application of an inductor is in the field of modern mobile communication that makes use of compact high-frequency equipment. Continued improvements in the performance of such equipment place continued emphasis on lowering the power consumption of the equipment, on reducing the size of the equipment, on increasing the frequency of the applications and on creating low noise levels.
Typically, inductors that are created on the surface of a substrate are of a spiral shape whereby the spiral is created in a plane that is parallel with the plane of the surface of the substrate. Conventional methods that are used to create the inductor on the surface of a substrate suffer several limitations. Most high Q inductors form part of a hybrid device configuration or of Monolithic Microwave Integrated Circuits (MMIC""s) or are created as discrete components, the creation of which is not readily integratable into a typical process of Integrated Circuit manufacturing.
The parameter by which the applicability of an inductor is typically indicated is the Quality (Q) factor of the inductor. The quality factor Q of an inductor is defined as Q=Es/El=F0L/R wherein Es is the energy that is stored in the reactive portion of the component, El is the energy that is lost in the reactive portion of the component, F0 is the resonant frequency of oscillation of the resonant circuit of which the inductor is a component, L is the inductance of the inductor and R is the resistance of the inductor. The higher the quality of the component, the closer the resistive value of the component approaches zero while the Q factor of the component approaches infinity. The quality factor Q is dimensionless. A Q value of greater than 100 is considered very high for discrete inductors that are mounted on the surface of Printed Circuit Boards. For inductors that form part of an integrated circuit, the Q value is typically in the range between about 3 and 10.
In typical applications, the redistribution inductor, created in a plane that is parallel with the surface of the substrate over which the inductor is created, has very low serial resistance. However, the conventional via that is provided between the inductor and the underlying metal contributes a finite value of resistance which forms a barrier in the effort to reduce the resistive value of the inductor and to thereby improve the Q value of the inductor. The invention addresses this concern in the creation of a planar inductor.
U.S. Pat. No. 6,054,329 (Burghartz et al.) shows a spiral inductor.
U.S. Pat. No. 5,539,241, (Adidi et al.) and U.S. Pat. No. 5,478,773 (Dow et al.) show related spiral inductors and via processes.
A principle objective of the invention is to reduce the resistive component of a spiral inductor.
A new method and structure is provided to connect a planar, spiral inductor to underlying interconnect metal, the patterned interconnect metal has been created over a semiconductor surface. A layer of dielectric followed by a layer of passivation is deposited over the semiconductor surface, including the surface of the underlying interconnect metal. Large first vias are created through the layers of passivation and dielectric. The large first vias align with the patterned interconnect metal, providing low-resistivity points of interconnect between the spiral inductor, which is created on the surface of the layer of passivation concurrent with the creation of the large first vias, and the patterned interconnect metal. A thick layer of polyimide is deposited over the surface of the layer of passivation, including the surface of the spiral inductor and the large first vias. The invention can further be extended by creating at least one second via through the thick layer of polyimide aligned with at least one of the created first vias. A patterned and etched layer of metal that fills the second via creates a re-distribution layer on the surface of the thick layer of polyimide for flip chip interconnects.